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april 2012 doc id 10209 rev 4 1/30 AN1882 application note designing with the l6926, high efficiency monolithic synchronous step-down regulator introduction this application note details the main features and application advantages of this new synchronous step-down regulator. after describing how the device works and the main features, a step-by-step design section is provided in order to aid in the selection of the external components and in the evaluation of the losses. the device performances are shown in terms of efficiency and thermal results. at the end, some application ideas are proposed. this new product, designed using bcdv technology, is a high efficiency monolithic synchronous step-down regulator capable of delivering up to 800 ma of continuous output current and to regulate the output voltage from 0.6 v up to v in thanks to the 100% duty cycle operation capability. the input voltage ranges from 2 v to 5.5 v. the control loop architecture is based on a constant frequency peak current mode, while high efficiency at light loads is achieved by a low consumption functionality. the very low quiescent current (25 a) and shutdown current (0.2 a) make the device very suitable to supply battery-powered equipment like pdas and hand-held terminals, dscs (digital still cameras) and cellular phones. the switching frequency is internally set at 600 khz, but the device can be externally synchronized up to 1.4 mhz. an internal reference voltage of 0.6 v (typ) allows the device to regulate a minimum output voltage of the same low value. the low mosfets r ds(on) ensures high efficiency at high output current. additional beneficial features are: hysteretic uvlo, ovp, constant current short-circuit protection, power good and thermal shutdown. the msop8 package allows significant space savings on the board. figure 1. application test circuit www.st.com
contents AN1882 2/30 doc id 10209 rev 4 contents 1 pins function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1.1 low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1.2 low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 system stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2.1 current loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.2 voltage loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 dropout operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 pgood (power good output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 adjustable output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 ovp (over-voltage protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 external components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.3 inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.4 compensation network (r1c3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 losses and efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.1 conduction losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.2 switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.3 gate charge losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AN1882 contents doc id 10209 rev 4 3/30 8 efficiency results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 buck boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2 white led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.1 driving white leds: buck topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2.2 driving white leds: boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2.3 driving white leds: buck/boost topology . . . . . . . . . . . . . . . . . . . . . . . . 26 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
list of figures AN1882 4/30 doc id 10209 rev 4 list of figures figure 1. application test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. pins connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. msop8 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. equivalent circuit for the voltage loop analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. equivalent circuits during the on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. equivalent circuit during the off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. valley current limit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12. thermal performance results: v in = 3.7 v v out = 1.8 v i out = 800 ma . . . . . . . . . . . . . . 20 figure 13. rds(on) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15. component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16. top side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 17. bottom side view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 18. schematic demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 19. low noises vs. low consumption efficiencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 21. efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 22. efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 23. positive buck boost application. 1 li-ion cell to 3.3 v@0.25 a . . . . . . . . . . . . . . . . . . . . . . 25 figure 24. buck topology schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 25. boost topology schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 26. buck boost topology schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 27. pwm brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 28. analog brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AN1882 pins function doc id 10209 rev 4 5/30 1 pins function figure 2. pins connection figure 3. msop8 package table 1. pin description n. name description 1 run shutdown input. when connected to a lower voltage than 0.5 v (down to gnd) the device stops working. when connected to a higher voltage than 1.3 v (up to vcc) the device is enabled. the pin must not be left floating 2 comp error amplifier output. a compensation network has to be connected from this pin to gnd. usually a 220 pf capacitor is enough to guarantee the loop stability (see related section) 3 vfb error amplifier inverting input, used to adjust the output voltage (from 0.6 v to vin) by an external divider. 4 gnd ground 5 lx switch output node. common point between high side and low side mosfets 6 v cc input voltage. the operating input voltage range is from 2 v to 5.5 v. an internal uvlo circuit realizes a 200 mv (typ) hysteresis 7 sync operating mode selector input. low consumption mode, when connected to a higher voltage than 1.3 v (up to vcc). low noise mode when connected to a lower than 0.5 v (down to gnd). synchronization mode when connected to an external appropriate clock generator. this pin must not be left floating 8 pgood power good comparator output. it is an open drain output. a pull-up resistor should be connected between power good and v o . the pin is forced low when the output voltage is lower than 90% of the regulated output voltage and goes high when the output voltage is greater than 90% of the regulated output voltage. if not used, the pin can be left floating.
block diagram AN1882 6/30 doc id 10209 rev 4 2 block diagram figure 4. block diagram
AN1882 functional description doc id 10209 rev 4 7/30 3 functional description the main loop uses constant frequency peak current mode architecture. each cycle, the high side mosfet is turned on, triggered by the oscillator, so that the current flowing through it increases with a slope fixed by the operating conditions. when the sensed current (a part of the high side current) reaches the output value of the error amplifier e/a, comp pin, the internal logic turns off the high side mosfet and turns on the low side one until the next clock cycle begins or the current flowing through it goes down to zero (zero crossing comparator). during the load transients, the voltage control loop keeps the output voltage in regulation changing the comp pin value, fixing a new turn off threshold. moreover, during these dynamic conditions the choke must not saturate and the inductor peak current must never exceed the maximum value. this value is function of the internal slope compensation (see related section). 3.1 modes of operation 3.1.1 low consumption mode at light load, the device operates in burst mode in order to keep the efficiency very high also in these conditions. while the device is not switching the load discharges the output capacitor and the output voltage goes down. the comp pin, due to the feedback loop, increases and when a fixed internal threshold is reached, the device starts to switch again. in this condition the peak current limit is set approximately in the range of 200 ma-400 ma, depending on the slope compensation (see related section). once the device starts to switch the output capacitor is recharged. the repetition time of the bursts depend on parameters like input and output voltages, load, inductor and output capacitors. between two bursts, most of the internal circuitries are off, so reducing the device consumption down to a typical value of 25 a. during the burst, the frequency of the pulses is equal to the internal frequency. 3.1.2 low noise mode in case the very low frequencies generated by the low consumption mode are undesirable, the low noise mode can be selected. the efficiency is a little bit lower compared with the low consumption mode conditions when working close to zero loads, while the trend is to reach the efficiency of low consumption mode for intermediate light loads. the device could skip some cycles in order to keep the output voltage in regulation. in the figure 5 and 6 the lcm and lnm typical waveforms are shown.
functional description AN1882 8/30 doc id 10209 rev 4 figure 5. low consumption mode figure 6. low noise mode measurement conditions: v in = 4.2 v; v out = 1.5 v; i out = 30 ma; l = 6.8 h; c in = 10 f; c out = 22 f; r c = 40 k ; c c = 330 pf in figure 19 is shown a comparison between the efficiency in low noise mode and the efficiency in low consumption mode. 3.2 system stability since the device operates with constant frequency peak current mode architecture, the voltage loop stability is usually not a big issue. for most of the applications a 220 pf connected between the comp pin and ground is enough to guarantee the stability. in case very low esr capacitors are used for the output filter, such as multilayer ceramic capacitors, the zero introduced by the capacitor itself can be shifted at a frequency well above the resonance frequency of the l-c filter and the loop stability could be affected. adding a series resistor to the 220 pf capacitor can solve this problem. the right value for the resistor can be determined by checking the load transient response voltage waveforms.
AN1882 functional description doc id 10209 rev 4 9/30 the current mode stability can be studied in two consecutive steps; first the inner loop is closed (current loop) and then the second loop stability is considered (voltage loop). 3.2.1 current loop compensation the selected control architecture brings many advantages: easy compensation with ceramic capacitors, fast transient response and intrinsic peak current measurement that simplify the current limit protection. a known drawback, however, is that the current loop becomes unstable, when the duty cycle exceeds 50%. this phenomenon is known as "sub-harmonic oscillation" and can be avoided by adding a slope compensation signal. due to this fact, the current limit of the device decreases when the slope compensation signal is applied. the slope compensation is internally implemented from a duty around 30% and figure 7 shows how the slope compensation affects the device current limit. figure 7. slope compensation the amount of slope compensation depends on the inductor current slope during the off time. this slope, for a given duty cycle, is inversely proportional to the inductor value. since the device can be synchronized at higher frequency, it is reasonable to calculate the inductor value in terms of it. finally, the input voltage affects the off time slope as well. this is obvious because, for a given duty cycle, the output voltage (and so the off time inductor current slope) is directly proportional to the input one. in order to better manage these issues, the amount of slope compensation does not depend only on the duty cycle but also on the switching frequency and the input voltage. table 2. suggested inductor values for different switching frequencies, at v in = 3.6 v and v out =1.8 v f sw [khz] minimum inductor value [h] 600 6.8 1000 3.6 1400 2.7
functional description AN1882 10/30 doc id 10209 rev 4 in the above tables are indicated the minimum inductor values that ensure the current loop stability with an input voltage of 3.6 v and 5 v. also there is a maximum inductor value above which the loop can become unstable. for example, if the inductor is too high the lc double pole returns in bandwidth. 3.2.2 voltage loop compensation ideally in a current mode control, after closing the current loop, the pole splitting effect separates the complex double pole due to the inductor and the output capacitor in 2 different poles; the pole due to the inductor shifts out of system bandwidth (i.e. the inductor ideally acts like a current source), while the pole due to the output capacitor remains inside the bandwidth. in figure 8 is shown the equivalent circuit used to study the voltage loop compensation: figure 8. equivalent circuit for the voltage loop analysis in the equation 1 the power stage transfer function is shown: equation 1 where r o is the output equivalent resistor load (v o /i o ) and esr is the series resistance of the output capacitors. it can be seen that the pole due to the output capacitor shifts in frequency based on the load value. table 3. suggested inductor values for different switching frequencies, at v in = 5 v and v out =3.3 v f sw [khz] minimum inductor value [h] 600 8.2 1000 5.6 1400 3.6 hs () v o s () i l s () --------------- - sc o esr 1 + () r o sc o esr r o + () 1 + ----------------------------------------------------- - = =
AN1882 functional description doc id 10209 rev 4 11/30 in order to have zero dc error in the voltage regulation, the feedback voltage loop is implemented with an integrator stage; the transfer function of the signal stage is shown in the equation 2 . equation 2 where g m is the integrator transconductance (250 s). the total gain loop is: equation 3 where a v is the current loop factor (1 typ.) and is the feedback resistor divider ratio (r 2 /(r 2 +r 3 ). once the gain loop is known the system will be stabilized with the compensation network as shown in the section 5.1.4 . gs () g m a v ----------- sc c 1 + sc c -------------------- - ? = g loop s () r o g m 1sesrc o + () sc c r c 1 + () a v sc c 1sc o esr r o + () + () ---------------------------------------------------------------------------------------------- =
short-circuit protection AN1882 12/30 doc id 10209 rev 4 4 short-circuit protection the device is provided by two limiting current circuitries, one on the high side and a second on the low side mosfet. due to the peak current mode architecture, the peak current flowing through the high side switch is accurately sensed. when this current reaches the peak current limit threshold, the internal high side mosfet is turned off. in this way, the on time, t on , is reduced and the output voltage decreases. the minimum t on can be around 200 ns (t min ). in case of short- circuit, the peak current could further increase because the intervention of the high side limiting current is not fast enough. in this case, the valley current limits eliminate the risks of device failure. to better understand this concept, it's useful to read the below considerations on the current variation through the inductor during the on and off time. equation 4 equation 5 when v out = 0 v, it can be seen that the inductor current doesn't decrease during the off time. therefore the current will increase step by step during each cycle in order to understand when this phenomenon will end, some real parameter must be considered. figure 9. equivalent circuits during the on time i on v in v out ? () l ---------------------------------- t on ? = (on time slope) i off v out l -------------- t off ? = (off time slope)
AN1882 short-circuit protection doc id 10209 rev 4 13/30 figure 10. equivalent circuit during the off time considering the figures above, in particular during the off time, in despite of the output voltage is zero, the output current generates, on the parasitic resistances, the voltage drop necessary to produce a negative slope. so, the higher will be the output current, the higher will be the negative slope during the off time; in this way, the inductor current will find a stable value. this value is given by: equation 6 where t min is the minimum on time, f sw is the switching frequency, r n and r p are the on resistance of the low side and high side mosfets respectively, r l is the inductor series resistance and r o is the equivalent output resistance. as it can be seen, in these extreme conditions, the maximum current value depends both on the application conditions (like vin and f sw ), the inductor parasitic resistor r l , and the mosfets r ds(on) r n and r p . it does not depend on the peak current limit at all. in order to limit the output current to a safe value even in extreme short-circuit conditions, a current limit has also been introduced on the low side mosfet: this operates as a valley current limit, as shown in figure 11 . the high side mosfet does not turn-on until the inductor current exceeds the valley current limit. this implies that, depending on the over current conditions, the device skips some cycles, so reducing the equivalent switching frequency in order to limit the output current. with this approach, the maximum peak current is definitively limited to: equation 7 i lim v in t min f sw ? () ? r n r l + () 1t min f sw ? ? () r p r l + () t min f sw ? () ? + ? [] ------------------------------------------------------------------------------------------------------------------------------- ----------------------- = i lim i valley v in t min l ---------------------- + =
short-circuit protection AN1882 14/30 doc id 10209 rev 4 figure 11. valley current limit protection 4.1 synchronization the device can be synchronized with an external signal from 500 khz up to 1.4 mhz through the internal pll. when the device is locked, the external signal and the high side turn on rising edges are aligned. in this case the low noise mode is automatically selected. the device will eventually skip some cycles in very light load conditions depending also on the input/output conditions. the internal synchronization circuit is inhibited in short-circuit and over-voltage conditions in order to keep the involved protections effective. the synchronization signal amplitude can range typically from 1 v to vcc and the duty factor can range typically from 20% to 80%. sometimes, if the synchronization signal duty cycle is very similar to the application duty factor, noise can be detected on the l x pin. in this case some practical solutions are: 1. change the synchronization signal duty factor 2. decrease the synchronization signal amplitude 3. add 20 pf capacitor between the comp pin and ground. the device switches at 600 khz (typ.) if no synchronization signal is applied. 4.2 dropout operation when the input voltage is a li-ion battery, the voltage ranges from a minimum of 3 v or less to 4.1 v - 4.2 v (depending on the anode material). in case the regulated output voltage is from 2.5 v and 3.3 v, the device can work in linear mode or dropout operation. the minimum input voltage necessary to ensure output regulation can be calculated as: equation 8 where rdson_hs_max is the maximum high side resistance and r l is the series inductor resistance. v inmin v o i o r ds on () hsmax r l + () ? + = ---
AN1882 short-circuit protection doc id 10209 rev 4 15/30 4.3 pgood (power good output) the pin is an open drain output and so, a pull up resistor should be connected to it. if the feature is not required, the pin can be left floating. a power good signal, low, is available, until the output voltage reaches the 90% of the final value. after that, the pgood signal goes high and the internal transistor goes off. 4.4 adjustable output voltage the output voltage can be adjusted by an external resistor network from a minimum value of 0.6 v up to the v in . the output voltage value is given by: equation 9 thanks to the very low fb leakage current (typ. 25 na), high r 3 , r 2 values can be chosen of hundreds of k increasing the system efficiency also at very low load. 4.5 ovp (over-voltage protection) the device has an internal output over-voltage protection. if the output voltage goes higher than 10% of its nominal value, the low side mosfet is turned on until the output voltage returns inside the nominal value tolerances. during the over-voltage circuit intervention, the zero crossing comparator is disabled so that the device is also able to sink current. 4.6 hysteretic thermal shutdown the device has also a thermal shutdown protection activated when the junction temperature goes above 150 c. in this case both the high side mosfet and the low side one are turned off. once the junction temperature goes back to about 95 c, the device restarts the normal operation. v out 0.6 1 r 3 r 2 ------ - + ?? ?? ? =
application information AN1882 16/30 doc id 10209 rev 4 5 application information 5.1 external components selection 5.1.1 input capacitor the input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current, neglecting the ripple across the inductor. the rms input current (flowing through the input capacitor) is: equation 10 where is the expected system efficiency, d is the duty cycle and io the output dc current. supposing =1 this function reaches its maximum value at d=0.5 and the equivalent rms current is equal to i o /2. the maximum and minimum duty cycles are: equation 11 equation 12 depending on the output voltage value the worst case can be with the maximum or minimum input battery voltage. usually the best choice for the input capacitor is the mlcc (multilayer ceramic capacitor) thanks to its very small size and very low esr. ta bl e 4 provides a list of some mlcc manufacturers. 5.1.2 output capacitor the output capacitor is very important to satisfy the output voltage ripple requirement. very small inductors values reduce size and cost of the application but increase the current ripple. this ripple, multiplied by the esr of the output capacitor, is the output voltage ripple. tantalum and ceramic capacitors are usually good for this purpose. ceramic capacitors have the lowest esr for a given size, so for very compact applications they are the best choice. poscap capacitors from sanyo are also a good choice for the output filter. below is a list of some capacitor manufacturers. table 4. recommended input capacitors manufacturer series cap value (f) rated voltage (v) esr@600 khz (m.) panasonic ecj 10 to 22 6.3 10 taiyo yuden jmk 10 to 22 6.3 10 i rms i o d 2d 2 ? -------------- - ? d 2 2 ------ - + ? = d max v o v inmin ------------------ = d min v o v inmax ------------------- - =
AN1882 application information doc id 10209 rev 4 17/30 5.1.3 inductor the inductor value fixes the ripple current flowing through the output capacitor. the ripple current is usually fixed at 20%-30% of the output current and is approximately obtained by the following formula: equation 13 for example, with v out = 3.3 v, v in = 4.2 v (li-ion battery fully charged), f sw = 600 khz and i o = 600 ma and i = 200 ma, the inductor value is about 6 h. the peak current through the inductor is given by: equation 14 it can be seen that if the inductor value decreases, the peak current (which has to be lower than the current limit of the device) increases. this peak current must be lower than the saturation current of the choke. this is particularly important when using ferrite cores because they can hardly saturate (the inductance value decreases abruptly when the saturation threshold is exceeded, causing an abrupt increase of the current flowing through it). the inductor should be selected also considering the system stability, (see the slope compensation paragraph). moreover the inductor selection should be made taking in account the inductor parasitic resistance, because a too high value can decrease the efficiency. in the following table some inductor manufacturers are listed. table 5. recommended output capacitors manufacturer series cap value (f) rated voltage (v) esr (m.) panasonic ecj 10 to 47 6.3 10 panasonic eef 22 to 47 6.3 60 to 90 taiyo yuden jmk 10 to 47 6.3 10 sanyo poscap tpa 47 to 100 6.3 80 to 100 table 6. recommended inductors manufacturer series inductor value (h) saturation current (a) coilcraft do1607c 6.8 to 15 0.72 to 0.96 dt1608c 6.8 to 15 0.6 to 1 lpo1704 6.8 to 10 0.8 to 0.9 do1606t 6.8 to 10 1 to 1.1 panasonic ell6rh 6.2 to 22 0.7 to 1.4 ell6gm 6.8 to 10 0.93 to 1.1 to ko d62cb 10 to 22 0.71 to 1.07 d62c 10 to 22 0.63 to 0.99 l v in v out ? () i ---------------------------------- t on ? = i pk i o i 2 ---- - + =
application information AN1882 18/30 doc id 10209 rev 4 5.1.4 compensation network (r 1 c 3 ) as it is shown in the section 3.2 the system stability can be studied with the loop transfer function given by the equation 3equation 3 . if the output capacitor is a ceramic type the zero due to the esr generally will be out of the system bandwidth, so the stability of the system will be ensured by the cancellation between the pole due to the output capacitor and the equivalent load and the r 1 c 3 zero. in the equation 15equation 15 , a simplified gain loop expression, valid around the transition frequency f t is given by: equation 15 supposing c 2 = 22 f, the transition frequency at 0 db equal to 30 khz (f t is equal to the system bandwidth), and the output voltage equal to 1.8 v the r 1 value can be calculated as: equation 16 the nearest standard e12 series value is r 1 = 47 k . the higher is the bandwidth, the faster will be the transient response but the bandwidth (and so the r 1 value) must be lower than f sw /10 to avoid the effect due to the sampling effect poles as mentioned in the section 3.2 . the zero due to the compensation network must be at the least 5 times before the frequency transition, so the c 3 value will be: equation 17 the nearest standard value is c 3 = 470 pf. if the output capacitors are tantalum type the esr zero is in the system bandwidth and it can be used to stabilize the system so the zero due to the compensation network will be useless (the c 3 is necessary to the integrator function). 5.2 losses and efficiency there are losses affecting the efficiency of the application. some of these losses are related to the device and others are related to the external components. the most important losses are listed below. 5.2.1 conduction losses these losses are basically due to the not negligible resistances of the internal switches and the external inductor. usually the current ripple across the inductor is negligible and so to estimate the conduction losses of the inductor, the average output current can be considered. the conduction losses of the switches depend also on the duty cycle of the application. the rms current flowing through the high side mosfet is (i o ) 2 d while the rms current flowing through the low side mosfet is (i o ) 2 (1-d). so, the total conduction losses are: g loop s () g m r 1 sc 2 ------------------ - = r 1 2 f t c 2 g m ------------------- = c 3 5 2 f t r 1 ------------------- 500pf = =
AN1882 application information doc id 10209 rev 4 19/30 equation 18 where r p and r n are the series resistance of the high side and low side mosfets respectively and r l the series resistance of the inductor. the conduction losses due to the esr of the input and output capacitors are usually negligible, particularly when using ceramic caps (very low esr). anyway, in case of high esr values for these caps, their conduction losses are: equation 19 where i is the current ripple flowing through the choke and d is the duty cycle of the application. the conduction losses are particularly important at high current cause they depends on its squared value. 5.2.2 switching losses the switching losses are due to the turn on and off of the internal high side mosfet. equation 20 where t on and t off are the turn-on and turn-off times of the internal high side switch. these are approximately in the range of 15 ns to 20 ns.this loss is important at high frequency. 5.2.3 gate charge losses the gate charge losses derive from switching the gate capacitance of the internal mosfets. the gate capacitances (c h for the high side mosfets and c l for the low side mosfets) are charged and discharged with the input voltage at the switching frequency. equation 21 these losses are also directly proportional to the switching frequency and input voltage but are usually negligible compared with the conduction and switching losses. p mos i o 2 r p d () r n 1d ? () r l + ? + ? () ? = p cin cout , i o 2 d1d ? () ? () esr cin i 2 12 ------- - esr cout ? + ?? = p switching v in i o f sw t on t off + () 2 ----------------------------------- - ?? ? = p gatecharge v in c h c l + () f sw ?? = -
thermal considerations AN1882 20/30 doc id 10209 rev 4 6 thermal considerations depending on the electrical application conditions (input voltage, switching frequency, and output current) and ambient temperature, the heat produced by device losses could increases the junction temperature over its absolute maximum rating. the following relation can estimate the junction temperature of the device: equation 22 where t a is the ambient temperature of the application, rth_ja is the thermal resistance junction to ambient of the package and ptot is the overall power dissipated by the device. rth_ja depends a little bit on the application board but it can approximately considered equal to 180 c/w. ptot is given by: equation 23 figure 12. thermal performance results: v in = 3.7 v v out = 1.8 v i out = 800 ma figure 13. r ds(on) vs. temperature for a better estimation of the power dissipated it can be useful to consider the mosfets r ds(on) variation with the temperature, shown in the figure 13 . t j t a r thja p tot ? + = - p tot p mos p switching p gatecharge ++ = -
AN1882 application board doc id 10209 rev 4 21/30 7 application board figure 14. application board demonstration board layout in the figures below the demonstration board layout is shown. figure 15. component placement
application board AN1882 22/30 doc id 10209 rev 4 figure 16. top side view figure 17. bottom side view demonstration board schematic the very small package and high switching frequency allows a very compact application. the demonstration board circuit is shown in figure 18 :
AN1882 application board doc id 10209 rev 4 23/30 figure 18. schematic demonstration board figure 19. low noises vs. low consumption efficiencies table 7. demonstration board part list reference part number description manufacturer c1 ecj3xboj106k 10 f 6.3 v panasonic c2 ecj4xboj226m 22 f 6.3 v panasonic c3 c0406c221j5gac 220 pf, 5% 50 v kemet r1 10 k 1% 0402 neohm r2 100 k 1% 0402 neohm r3 200 k 1% 0402 neohm r4 100 k 1% 0402 neohm l1 ell6gm6r8m 6.8 h 1.1 a panasonic
efficiency results AN1882 24/30 doc id 10209 rev 4 8 efficiency results some efficiency results are shown below. figure 20. efficiency vs. output current figure 21. efficiency vs. output current figure 22. efficiency vs. output current
AN1882 application ideas doc id 10209 rev 4 25/30 9 application ideas 9.1 buck boost topology in portable applications, the input voltage changes significantly due to the battery discharge profile, which often depends on parameters like temperature, discharge rate, battery ageing, etc. moreover, in certain applications, the output voltage requirements can also change. this could imply that is not possible to provide the desired regulated output voltage by using the simple buck topology. this problem is often present, for example, in systems using a single li-ion cell, whose voltage profile changes from 4.2 v down to 2.7 v or less. in fact, in these systems, a 3.3 v output is normally required to power processor i/o, memory and logic. adopting the buck topology, the 3.3 v output can be regulated until the battery voltage is approximately 3.4 v, also depending on the minimum dropout of the regulator. depending on the battery type and conditions, this would leave unused some 20%-30% of its capacity. another application, even more critical, is the power management of 3g phones, where a 3.7 v or more can be required to power the rf power amplifier (pa). in order to use the full battery capacity also in these applications, a positive buck/boost topology can be used. figure 22 shows how to implement it. this topology can be more suitable, compared to a standard buck, depending on the battery discharge profile and the load conditions. in fact, the efficiency loss of the buck/boost topology can be translated into an equivalent loss in battery capacity. this can then be compared with the gain in battery capacity due to the fact that it is used over the full voltage range. figure 23. positive buck boost application. 1 li-ion cell to 3.3 v@0.25 a 9.2 white led white leds are now widely used both for lcd backlighting and for illumination. since their brightness is proportional to the current flowing through them, a current control loop must be implemented instead of a voltage one. the device can be used in current control architecture by simply inserting a sense resistor between the fb and gnd pins and connecting the led in series with it. the loop will set 0.6 v across the sense resistor, and so, a constant current flowing through the led. the current, and by consequence, the brightness, can be adjusted by changing the resistor value or the voltage across it (by partitioning the fb pin voltage). the forward voltage across a white led is approximately 3.6 v and so, depending on the input source, appropriate topologies must be used.
application ideas AN1882 26/30 doc id 10209 rev 4 9.2.1 driving white leds: buck topology the simple buck topology can be used when the input voltage source is higher than approximately 4.5 v that is the case, for example, with the usb bus. figure 24. buck topology schematic in this case, the maximum device current (800 ma, continuous) can be delivered to the led. moreover, in this topology, the efficiency is maximized. 9.2.2 driving white leds: boost topology when the input voltage source is always lower than 3 v (that is the case, for example, of 2 cells of a nimh battery) a boost topology must be implemented, as shown in figure 24 . figure 25. boost topology schematic in this case, according to the boost topology, the maximum current that can be delivered depends on the duty cycle. the relationship between the output current and the internal switch current (assuming a negligible current ripple and 100% efficiency) is given in equation 24 :
AN1882 application ideas doc id 10209 rev 4 27/30 equation 24 this topology is possible because the input source is a battery, and thus must not be referred to ground. a drawback of this approach, intrinsic to the boost topology, is that a path between the input and output is always present. this does not allow effective short-circuit protection and can generate a battery discharge also when the device is turned off. 9.2.3 driving white leds: buck/boost topology in case a single li-ion cell is used at the input, a buck/boost topology can be used, as shown in figure 25 . figure 26. buck boost topology schematic the relationship between the output current and the switch current is the same as the boost topology. an advantage of this topology compared with the boost, is that when the device is turned off, there is no current path between the input and the output. this allows an effective short-circuit protection and minimizes the current drawn from the battery when the device is turned off. a dimming control can be developed by turning on and off the device with a frequency of around 100-200 hz in order to avoid led flickering. another way to implement the led dimming is to reduce the voltage drop across the resistor in series to the led to a partition of the fb voltage. the figure 27 and figure 28 shows the relative circuits. i out is witch 1d ? () =
application ideas AN1882 28/30 doc id 10209 rev 4 figure 27. pwm brightness control figure 28. analog brightness control both of solutions change the output current by changing then fb voltage. in the figure 26 is used a dc voltage; instead in the figure 27 is used the average voltage coming from the pwm signal.
AN1882 revision history doc id 10209 rev 4 29/30 10 revision history table 8. document revision history date revision changes 03-nov-2007 1 initial release 08-oct-2008 2 document reformatted. no content change changed: figure 13 26-feb-2009 3 modified: section 5.1.1 13-apr-2012 4 modified: l1 part number and description table 7 on page 23
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